1. Field of the Invention
The present invention relates to a semiconductor memory device and to a semiconductor device.
More specifically, the present invention relates to a semiconductor memory device and a semiconductor device structured to protect its data portion against a surge current.
2. Description of the Background Art
FIG. 30 is a partially omitted from plan view showing a layout of a conventional dynamic random access memory (hereafter referred to as a DRAM). In the figure, memory mats 51 are provided at four corners of a rectangular chip, respectively. A row recorder 52 is provided along a longer side of each memory mat 51, and a column decoder 53 is provided along a shorter side of each memory mat 51.
A plurality of pads are arranged in one line at a peripheral circuit region 54 at the center of the chip. A ground potential VSS is externally applied to pads 1.1, 1.2 and 1.3. A power supply potential VCC is externally applied to pads 2.1, 2.2 and 2.3. Pads 3.1 to 3.K are used for data signal input/output. Control clock signals /RAS, /CAS, . . . are applied to pads 4.1 to 4.M. Address signals A1 to AN are externally applied to pads 5.1 to 5.N.
Along the plurality of pads, three power supply lines 2ALVCC, 2ALVBB and 2ALVSS are provided. To power supply line 2ALVCC, the power supply potential VCC is applied externally through pads 2.1, 2.2 and 2.3. A negative power supply VBB is applied from an internal power supply circuit (not shown) provided in the chip to power supply line 2ALVBB. The ground potential VSS is applied externally to power supply line 2ALVSS through pads 1.1, 1.2 and 1.3.
An internal protecting circuit for protecting an internal circuitry of the DRAM against an externally applied surge current is provided in each pad.
FIG. 31 is a schematic diagram showing the structure of the internal protecting circuit 9 provided in each of pads 4.1 to 4.M and 5.1 to 5.N. Referring to the figure, the internal power protection circuit 9 includes two resistance elements 6 and 8 connected in series between a pad (for example, 5.2) and an internal circuitry of the DRAM, and a field transistor 7 connected between a connection node of the two resistance elements 6 and 8 and a node of the ground potential VSS (hereinafter referred to as the ground node). Field transistor 7 has its gate connected to the ground node.
The surge current input to pad 5.2 is attenuated by resistance element 6. The surge current which has passed through resistance element 6 flows out to the ground node through field transistor 7 by a punch through. The remaining surge current which did not flow out to the ground node is further attenuated by resistance element 8 and flows to an internal circuitry. Therefore, the internal circuitry can be protected against the surge current.
FIG. 32 is a partially omitted view of the portion including pads 4.1 to 4.M and 5.1 to 5.N of FIG. 30, shown in enlargement. Near each of the pads 4.1 to 4.M and 5.1 to 5.N, an n type well region NW for the internal protecting circuit 9 is provided, and two p type well regions PW2 and PW2 are formed in each n type well region NW. Power supply lines 1ALVCC, 1ALVBB and 1ALVSS are provided corresponding to each of the pads 4.1 to 4.M and 5.1 to 5.N.
To each n type well region NW, the power supply potential VCC is applied from power supply line 2ALVCC to power supply line 1ALVCC. To each of the p type well regions PW1 and PW2, the power supply potential VBB is applied from power supply line 2ALVBB through power supply line 1ALVBB. To each p type well region PW1, the ground potential VSS is further applied from power supply line 2ALVSS through power supply line 1ALVSS.
For connecting adjacent well regions NW and PW2, power supply lines 1ALVBB' and 1ALVCC' are provided. The plurality of p type well regions PW2 corresponding to pads 4.1 to 4.M are connected to each other by means of power supply line 1ALVBB'. The plurality of p type well regions PW2 corresponding to pads 5.1 to 5.N are connected to each other by power supply line 1ALVBB'. The plurality of n type well regions NW corresponding to pads 5.1 to 5.N are connected to each other by power supply line 1ALVCC'. The plurality of n type well regions NW corresponding to pads 4.1 to 4.M are not connected to each other by the power supply line 1ALVCC', because of a reason in a layout.
FIG. 33 is enlarged view of a portion including n type well regions NW of FIG. 32. Two p type well regions PW1 and PW2 are formed separated from each other in n type well regions NW. A field transistor 7 of internal protecting circuit 9 is formed in p type well region PW1, and resistance element 8 of internal protecting circuit 9 is formed in p type well region PW2. Field transistor 7 has its gate and source connected to power supply line 1ALVSS. The p type well region PW1 including field transistor 7 is formed separate from p type well region PW2 including resistance element 8 in accordance with a general method of design in which arrangement is performed element by element.
Referring to FIGS. 34 and 35, the structure of internal protecting circuit 9 will described in greater detail. FIG. 34 is an enlarged view of pad 5.2 and portions therearound of FIG. 32, and FIG. 35 is a cross section taken along the line 35--35 of FIG. 34.
Referring to FIGS. 34 and 35, in the DRAM chip, a so-called triple well structure is employed. More specifically, at a surface of a p type silicon substrate 20, an n type well region BNW is formed, and at its surface p type well region PW1 and PW2 are formed. Along p type well regions PW1 and PW2, n type well region NW is formed, and p type well regions PW1 and PW2 are separated from p type silicon substrate 20. At the surface of n type well region NW, a band shaped n.sup.+ type potential fixed region 21 is formed.
The n.sup.+ type drain region 7d of field transistor 7 is formed at the center of the surface of p type well region PW1, and n.sup.+ source region 7s is formed surrounding n.sup.+ drain region 7d. A band shaped p.sup.+ type potential fixed region 22 is formed along the outer periphery of p type well region PW1.
At the central portion of the surface of p type well region PW2, an n.sup.+ type diffusion resistance region 8 is formed. The n.sup.+ type diffusion resistance region 8 constitutes the resistance element 8 of internal protecting circuit 9. Around the outer periphery of p type well region PW2, a p.sup.+ type potential fixed region 23 is formed.
An IF transistor 12 for testing state of connection of pad 5.2 and a bonding wire is also formed in p type well region PW2.
On silicon substrate 20, a polycrystalline silicon layer BL, a lower aluminum interconnection layer 1AL and an upper aluminum interconnection layer 2AL are formed successively. By polycrystalline silicon layer BL, resistance element 6 and interconnections 10 and 11 for cross under are formed. By lower aluminum interconnection layer 1AL, power supply lines 1ALVCC1 to 3, 1ALVCC', 1ALVBB, 1ALVBB', 1ALVSS1, 1ALVSS2 and signal lines 1ALSL1 to 3 are formed. By the upper aluminum interconnection layer 2AL, pad 5.2 and power supply lines 2ALVCC, 2ALVBB and 2ALVSS are formed.
Pad 5.2 is connected to one end of resistance element 6 through signal line 1ALSL1. Resistance element 6 has its the other end connected to one end of resistance element 8 and to n.sup.+ type drain region 7d of field transistor 7 through signal line 1ALSL2. Resistance element 8 has the other end connected to the internal circuitry of the DRAM through signal lines 1ALSL3. Power supply line 1ALVSS1 and 1ALVSS2 also serve as gate electrodes 7g1, 7g2 of field transistor 7. Power supply lines 1ALVSS1 and 1ALVSS2 are connected to power supply line 2ALVSS.
Power supply lines 1ALVCC1 to 3 are formed on n.sup.+ type potential fixed region 21 of n type well region NW, and connected to n.sup.+ type potential fixed region 21 through a contact hole. Power supply lines 1ALVCC1 and 1ALVCC2, and 1ALVCC2 and 1ALVCC3 are connected to each other by interconnections 10 and 11, respectively. Power supply lines 1ALVCC1 and 1ALVCC3 are connected to power supply line 2ALVCC. Power supply line 1ALVCC2 has both ends connected to power supply line 1ALVCC2 corresponding to pads 5.1 and 5.3 through power supply line 1ALVCC', respectively.
Power supply line 1ALVBB is formed along p.sup.+ type potential fixed regions 22 and 23 of p type well regions PW1 and PW2, and connected to p type potential fixed regions 22 and 23 through contact holes. Power supply line 1ALVBB is connected to power supply line 2ALVBB. Power supply line 1ALVBB is connected to power supply line 1ALVBB corresponding to adjacent pads 5.1, 5.3 through power supply line 1ALVBB' passing above interconnections 10 and 11, respectively.
Structures near remaining pads 5.1, 5.3 to 5.N are similar. The structure near pads 4.1 to 4.M is also similar, except that power supply lines 1ALVCC2 are not connected by power supply line 1ALVCC'.
In FIG. 34, the distance Ly between an end of the resistance element 8 on the input side (connected to n.sup.+ type drain region 7d of field transistor 7) and the power supply line 1ALVCC2 is smaller than the distance Lx between the end of resistance element 8 on the input side and the power supply line 1ALVCC3.
FIG. 36 shows a structure of a pad 5.2 and portions therearound of another conventional DRAM not employing the triple well structure. FIG. 37 is a cross section taken along the line 37--37 of FIG. 36, and FIG. 38 is a cross section taken along the line 38--38 of FIG. 36.
Referring to the figures, in the DRAM, n.sup.+ type drain region 7d and n type source region 7s of field transistor 7 and n.sup.+ type diffusion resistance region 8 are directly formed at the surface of p type silicon substrate 20, and wells PW and NW are not formed. The n.sup.+ type drain region 7d, n.sup.+ type source region 7s and n.sup.+ type diffusion resistance region 8 are separated from each other by a field oxide film 24. A resistance element 6 is formed by a polycrystalline silicon layer BL, signal lines 1ALSL1 to 3 are formed by lower aluminum interconnection layer 1AL, and pad 5.2 is formed by an upper aluminum interconnection layer 2AL.
Pad 5.2 is connected to one end of signal line 1ALSL1 through a contact hole CH, and the other end of signal line 1ALSL1 is connected to one end of resistance element 6 through contact hole CH. The other end of resistance element 6 is connected to one end of signal line 1ALSL2 through a contact hole CH, and the other end of signal line 1ALSL2 is connected to n.sup.+ type drain region 7d of field transistor 7 and to one end of n.sup.+ type diffusion resistance region 8 through a contact hole CH. The other end of n.sup.+ type diffusion resistance region 8 is connected to single line 1ALSL3 through a contact hole CH, and the other end of signal line 1ALSL3 is connected to the internal circuitry of the DRAM.
The DRAM is similar to the DRAM shown in FIGS. 30 to 35 except that the triple well structure is not employed.
For simplicity, the gate electrodes 7g1 and 7g2 of field transistor 7 and IF transistor 12 shown in FIG. 36 are omitted in FIG. 36.
Further, in FIGS. 30 to 35, field oxide film 24 shown in FIG. 37 and 38 are omitted for simplicity.
FIG. 39 is a cross section showing a still another conventional DRAM structure not employing the triple well structure but employing a trench separation structure, which corresponds to FIG. 37. In the DRAM, n.sup.+ type drain region 7d, n.sup.+ type source region 7s and n.sup.+ plus type diffusion resistance region 8 are separated from each other by a trench separation region 25. Trench separation region 25 is formed by forming at the surface of silicon substrate 20, a trench deeper than a junction portion between n.sup.+ type drain region 7d and silicon substrate 20, and by filling the trench with an insulator. The DRAM is similar to that shown in FIGS. 36 to 38 except that it employs the trench separation structure.
In the chip shown in FIGS. 30 to 35 employing a triple well structure, a surge current was applied to each of the pads 4.1 to 4.M and 5.1 to 5.N for testing the surge immunity of the chip. Then it was found that the internal protecting circuit 9 corresponding to pads 5.1 to 5.N was more susceptible to damage than the internal protecting circuit 9 corresponding to pads 4.1 to 4.M. The reason for this may be the fact that the current value flowing from the input side end of resistance element 8 to power supply line 1ALVCC2 differ dependent on the presence/absence of power supply line 1ALVCC'.
Further, it was found that surge immunity of the chip shown in FIGS. 30 to 35 employing the triple well structure has smaller surge immunity than the chip shown in FIGS. 36 to 38 not employing the triple well structure. The reason for this may be the fact that in the chip employing the triple well structure, surge current leaking from resistance element 8 diffuses only in the well regions PW1, NW and BNW, while in the chip not employing the triple well structure, the surge current leaking from resistance element 8 diffuses to the entire signal substrate 20. In other words, it is because of the difference of the capacity of portions absorbing the surge current.
In the chip shown in FIGS. 36 to 38 not employing the triple well structure, it was found that of the junction surfaces between n.sup.+ type drain region 7d, n.sup.+ type diffusion resistance region 8 and the silicon substrate 20, the portion corresponding to the junction between n.sup.+ type drain region 7d, n type diffusion resistance region 8 and contact hole CH (for example, the portion Q of FIG. 38) tends to be broken. A reason for this may be the fact that aluminum atoms of contact hole CH diffuse into n type drain region 7d and n.sup.+ type diffusion resistance region 8, and that there is a large difference in impurity concentration between n.sup.+ type region 7d, n.sup.+ type diffusion resistance region 8 and silicon substrate 20, so that electric field at the portion Q increases when the surge current flows, resulting in a leak path formed by large current flowing through the portion Q.
The chip shown in FIG. 39 employing not the triple well structure but the trench separation structure has low capability of absorbing surge current. The reason for this may be the fact that the current flowing through the base of npn bipolar transistor formed in the horizontal direction below the field transistor 7 is intercepted by trench separation region 25, and therefore npn bipolar transistor comes to have reduced current drivability.